library ieee;
use ieee.std_logic_1164.all;

entity execute is
	port ( RD1E, RD2E, PCPlus4E, SignImmE : in std_logic_vector (31 downto 0);
		   RtE, RdE : in std_logic_vector (4 downto 0);
		   RegDst, AluSrc : in std_logic;
		   AluControl : in std_logic_vector(2 downto 0); -- el enunciado miente, alucontrol es si o si un vector de 3 bits... 
		   AluOutE, WriteDataE, PCBranchE : out std_logic_vector (31 downto 0);
		   WriteRegE : out std_logic_vector(4 downto 0);
		   ZeroE : out std_logic);
end entity;

architecture execute_arch of execute is

	component mux2
    port (d0, d1 : in std_logic_vector(31 downto 0);
               s : in std_logic;
               y : out std_logic_vector(31 downto 0));
    end component;
    component adder
	port (	a, b : in std_logic_vector(31 downto 0);
			y : out std_logic_vector(31 downto 0));
    end component;
    component alu
    port (a, b : in std_logic_vector(31 downto 0);
		  alucontrol : in std_logic_vector(2 downto 0);
          y : out std_logic_vector(31 downto 0);
          zero : out std_logic);
    end component;
    component sl2
    port (a : in std_logic_vector(31 downto 0);
          y : out std_logic_vector(31 downto 0));
	end component;
	
	--signal PCnext, PC', SrcBE, ALUResult, SignImm, PCBranch, WriteData, ReadData, PCPlus4, PCJump, WriteReg : std_logic_vector(31 downto 0);
	signal tmp, tmp2, tmp3, SignImm, SrcBE : std_logic_vector(31 downto 0);
	
	begin
	
	tmp2 <= "000000000000000000000000000" & RtE; -- mux2 fue pensado para vectores de 32 bits...
	tmp3 <= "000000000000000000000000000" & RdE; -- mux2 fue pensado para vectores de 32 bits...
	
	mux_rd : mux2 port map (d0 => tmp2, d1 => tmp3, s => RegDst, y => tmp);
	
	WriteRegE <= tmp(4 downto 0);
	
	mux_alu : mux2 port map (d0 => RD2E, d1 => SignImmE, s => AluSrc, y => SrcBE);
	
	sl2_map : sl2 port map (a => SignImmE, y => SignImm);
	
	alu_map : alu port map (a => RD1E, b => SrcBE, alucontrol => AluControl, y => AluOutE, zero => ZeroE);
	
	adder_E : adder port map (a => SignImm, b => PCPlus4E, y => PCBranchE);
	
end architecture;
